The present invention relates to a memory circuit constituted of semiconductor elements, and more particularly to a memory circuit employing insulated gate field effect transistors (IGFET's) fabricated on a semiconductor chip.
In dynamic random access memories employing IGFETs (hereinafter abbreviated as dynamic RAM) a 2-clock multi-address system has been employed in a 16 K-bit memory as well as in a 64 K-bit memory both with a 16-pin package structure. The details of this multi-address system are disclosed in the specification and drawings of U.S. Pat. No. 3,969,706 issued to Robert J. Proebsting et al on July 13, 1976. Basically, two input clocks, that is, a row strobe signal defined as ROW ADDRESS STROBE (abbreviated as RAS) and a column strobe signal defined as COLUMN ADDRESS STROBE (abbreviated as CAS) are generated in a predetermined sequence. In the following description, an example is adopted where N-channel IGFET's are used and RAS and CAS are assumed to be active when they are low signals. At first, when RAS becomes active by turning it from a high level to a low level, input levels at address terminals at that time point are incorporated in the memory and held therein as row address inputs which are used to select a word line and refresh memory cells connected to the selected word line. After completion of latching of address inputs in response to RAS, CAS becomes active by being turned from a high level to a low level to thereby incorporate the input levels at the address terminals at this time in the memory as column address inputs. Depending upon a level of a write control signal defined as WRITE ENABLE (abbreviated as WE), if WE is not at its active level, i.e., it remains high, then data read-out from the selected memory cell is effected so that the data appear at a data output terminal. If WE is at its active level, on the other hand, then the data at a data input terminal at the time point is written in the selected memory cell.
Recently a refresh operation called "HIDDEN REFRESH" has been employed in the multi-address system. This refresh operation is as follows:
After read-out data from a selected memory cell has been obtained by sequentially making RAS and CAS active the refresh operations for the memory cells on the different word lines can be sequentially effected while maintaing the read-out data at the data output terminal by repeatedly making RAS active and maintaining CAS at the low level. In other words, during the period when the read-out data is effectively revealed, the refresh operation can be effected simultaneously, and this operation is thus called HIDDEN REFRESH. However, HIDDEN REFRESH must be performed under the condition that WE is maintained at the high level i.e. inactive level, and hence this mode of operation lacks flexibility in control.